Selective Formation of GaAs and InAs Quantum Dots

T. Fukui, C-K. Hahn, H. An, F. Nakajima and J. Motohisa

Research Center for Interface Quantum Electronics, Hokkaido University,

N13, W8, Sapporo, 060-8628, Japan

Tel:+81-11-706-6870, Fax:+81-11-716-6004,

We demonstrate a novel formation method of GaAs and InAs quantum dot structures using selective area metalorganic vapor phase epitaxy (MOVPE), and their applications to single electron devices.

GaAs pyramidal structures with four {110} sidewalls were grown on SiNx masked (001) GaAs substrates, which have square openings, formed by electron beam lithography and wet chemical etching. InAs single or multiple quantum dots were grown on these GaAs pyramids. InAs QDs were preferentially formed near the top of GaAs pyramidal structures probably caused by the high-density step and kink sites as well as the stress. The number of InAs dots can be controlled by the mask pattern and the top shape of underlying GaAs pyramids. Optical properties of InAs quantum dots were investigated by photoluminescence (PL) and excitation photoluminescence (PLE).

GaAs QDs connected with quantum wires (QWRs) was also grown on GaAs masked substrate, and was applied to single electron transistors (SETs) and their circuits. The SiNx coated substrates had a wire-like opening with width modulation. GaAs trapezoidal growth occurred at wire-like opening area, and (001) plane appeared on the top portion of the whole structure. AlGaAs/GaAs modulation doped heterostructures were grown on top of GaAs trapezoid. Due to the width modulation on the wire, the GaAs quasi-one dimensional electron gas (Q-1DEG) channel had a variation in its thickness and width. This led to the natural formation of a quantum dot at the wide cannel area and two tunneling barriers beside a dot, which were connected to quantum wires. On top of a dot part, Al Schottky gate electrode was formed. Clear Coulomb gaps and their modulation by gate voltage was observed near the pinch-off voltage at 2K, which indicates successful formation of SET. Next, resistance-loaded SET inverter circuit proposed by K. K. Likharev was formed. Load resistance was formed at wire part by squeezing the channel by Al Schottky gate. Output electrode was formed between SET and resistor. As gate voltage (input voltage) was swept to the negative gate voltage, output voltage smoothly increased, clearly showing the inverter operation.

These selective area growth techniques can be applied to form single electron memory and circuits.